Descripción de la vacante
Permanent contract
Spain
Functional Verification Engineer en España is listed on Jobeax. Browse 80,000+ vacancies available.
Experience in the following are a plus:
We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.
If you feel identified with Openchip, please contact us. We can offer a competitive compensation package in a flexible work schema that will help you to keep a balance between your personal and professional life.
At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential - regardless of race, gender, ethnicity, sexual orientation, or gender identity.
As a Functional Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.
Reading and analysing the system requirements and architecture requirement documents.
Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.
Using the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking,...).
Create and execute testcases to verify the functionality, performance, and robustness in embedded C and SV.
Identify, isolate, and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams.
Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.
Participation to verification methodology improvements.
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